latch up jedec
STANDARD. IC Latch-Up Test. JESD78B. (Revision of JESD78A, November 2005). DECEMBER 2008. JEDEC SOLID STATE TECHNOLOGY ASSOCIATION ... ,The equivalent circuit for negative input/output I-test latch-up testing. 14. 7. The equivalent circuit for Vsupply over-voltage test latch-up testing. 15. Annex A ...
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 latch up jedec 相關參考資料
IC LATCH-UP TEST | JEDEC
The purpose of this standard is to establish a method for determining IC latch-up characteristics and to define latch-up detection criteria. Latch-up characteristics ... https://www.jedec.org JEDEC STANDARD
STANDARD. IC Latch-Up Test. JESD78B. (Revision of JESD78A, November 2005). DECEMBER 2008. JEDEC SOLID STATE TECHNOLOGY ASSOCIATION ... http://caxapa.ru JEDEC STANDARD IC Latch-Up Test JESD78D
The equivalent circuit for negative input/output I-test latch-up testing. 14. 7. The equivalent circuit for Vsupply over-voltage test latch-up testing. 15. Annex A ... https://www.jedec.org latch-up (of a voltage regulator) | JEDEC
latch-up (of a voltage regulator). A condition in which a regulator has been driven into the foldback limiting mode and will not respond to the removal of the ... https://www.jedec.org Latch-up - Standards & Documents Search | JEDEC
This standard covers the I-test and Vsupply overvoltage latch-up testing of ... for determining IC latch-up characteristics and to define latch-up detection criteria. https://www.jedec.org Latch-Up White Paper - Texas Instruments
This document describes and discusses the topic of CMOS Latch-Up ranging from theory to testing of products. The recently proposed modifications to JEDEC ... http://www.ti.com latch-up | JEDEC
latch-up. A state in which a low-impedance path, resulting from an overstress that triggers a parasitic thyristor structure, persists after removal or cessation of the ... https://www.jedec.org Search by Keyword or Document Number - JEDEC
10 items - This standard covers the I-test and Vsupply overvoltage latch-up testing of integrated circuits. The purpose of this standard is to establish a method for ... https://www.jedec.org single-event latch-up (SEL) | JEDEC
single-event latch-up (SEL). An abnormal high-current state in a device caused by the passage of a single energetic particle through sensitive regions of the ... https://www.jedec.org trigger pulse (in latch-up testing) | JEDEC
trigger pulse (in latch-up testing). A positive or negative current pulse or voltage pulse applied to any terminal under test in an attempt to induce latch-up. https://www.jedec.org |